K. P. Sridhar ¹, D. Muralidharan ¹

Affiliations
1 VLSI Design, School of Computing, SASTRA University, IN

Abstract

Microelectronic crypto devices contain intellectual property like secret data to be protected against side channel attack. Scan chain based attacks come under the category of side channel attack where the hackers attack a scan path through observing and comparing the relationship between intermediate hamming distances values for different test vector patterns. Hence our novel hamming model should overcome the scan based attack and should not give any correlation relationship in hamming distance by providing the similar intermediate values for all test vector patterns which are obtained through an optimal way of inserting Optimal Scan Flip Flop (OSFF) randomly to the scan path chain. Implementation of our proposed integrated circuits is written in Verilog and synthesised with XILINX Spartan III FPGA. The report is compared with Robust Scan Flip Flop (RFSS) hamming model to estimate the overhead of component minimized in OSFF.

Keywords

Crypto Cores, Chip Security, FPGA, Verilog, VLSI Testing

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N. Balameena ¹, D. Muralidharan ²

Affiliations
1 School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur, Tamil Nadu, IN
2 School of Computing, Information Technology, SASTRA University, Thirumalaisamudram, Thanjavur, Tamil Nadu, IN

Abstract

To implement automation testing for testing the telecom node commands in the wireless network management system. The main objective of this project is to perform automation testing for the various mode commands used in the wireless telecom nodes that plays vital role in enterprise applications implementation. There is various software testing methods that plays an important role in program progress lifestyles cycle. At present many programs were written based on internet utility which runs in a web Browser. This monetary relevance of net founded software increases the need of controlling and increases its satisfactory. In this modern technology world, manual testing of various telecom node commands became a time consuming and tedious process. Further, it is not effective in detecting the defects in large and time bound projects. In order to solve such problem, it is important to introduce a framework for automation testing. The assurance for quality of a system relies on automated checking that decreases the cost of testing and improves work effectively. A style of net centered techniques and functions are confirmed by automated testing instruments. To select the satisfactory method for a mission, quite a lot of issue like integration should be weighed and viewed against the time, cost and efficiency. Additionally the selected tool should suite the implementation and design of a utility.

Keywords

Automation Testing, Manual Testing, Network Management System, Telecom Node Commands, Wireless Telecom Nodes.

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S. Anu Karpaga ¹, D. Muralidharan ²

Affiliations
1 School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur - 613401, Tamil Nadu, IN
2 School of Computing, Information Technology, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

Network on-Chip (NoC) is a novel technology which is used to make the interconnections between the components available in the System on Chip (SoC) design. This technology of NoC is defined and used in two varied forms as buffered and bufferless NoC. Bufferless NoC, a predominant type of network on chip, is used to reduce the cost efficiently by removing input buffers of the router. However, it is evident that this performance gets jammed at high loads because of the increase in the network contentions and deflection of packets in huge amount. To reduce the amount of deflection and to buttress the flow, Clumsy Flow Control (CFC) is used in the bufferless NoC. In this paper, a novel proposal has been propounded into the pipelining mechanism keeping in mind the flawless flow control needed for the bufferless NoC to decrease the impact of deflection routing and to increase the throughput with high injection rate. Employing the pipelining technique into the existing flow control increases the frequency which in turn, is responsible for high throughput. Implementation of the aforementioned pipelining mechanism is done in two stages in the bufferless NoC which helps to increase the throughput as well as the injection rate. Finally, the application with its pipelined implementation, as proposed, will be mapped onto the NoC architecture by using the CFC.

Keywords

Bufferless NoC, CFC, Network on Chip, Pipeline, Router.

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S. Aishwarya ¹, D. Muralidharan ²

Affiliations
1 School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur - 613401, Tamil Nadu, IN
2 School of Computing, Information Technology, SASTRA University, Thirumalaisamudram, Thanjavur - 613401, Tamil Nadu, IN

Abstract

On chip communication is now an upcoming technology; whereOn-chip interconnections are becoming tedious as they need to assure reliability, power, speed and scalability issues. Systems on chips, (SoCs), are so intricate that they oblige new interconnection techniques. Networks on Chip (NoCs) have paved way to resolve these problems. As application is becoming complex they require good design for greater bandwidth and performance which lead to 3D NoC. 3D NoC provide best solutions to connect as many functional elements on-chip over 2D NoC. Data flow NoCs can be categorized into: packet switched and circuit switched NoCs. The paper focus on simultaneous circuit and packet switching to benefit from two methods which ensures low latency and more resource utilization. Here in this paper, the circuit switched NoC is much concentrated where we implement our ideas in area like circuit setup method. Here we bring in a new method for guaranteed Quality of Service (QoS) known an efficient path establishment mechanism in circuit switching in 3D Torus topology. Torus topology aims to produce less latency of other topologies, where the path is estimated based on to the destination node layers and position. This paper is more advantageous where it can get switched between to different layers and position in which destination is placed. As of 3D NoC with increased number of nodes it ensureslow power, low latency, increase hardware integration, improved throughput and enables multi core processing and also resolves scalability crisis. It can operate on both packet and circuit switching which reduces both cost and operational expenses. Analysis on latency, power and throughput is made for 3D hybrid integration which provides better solutions. Optic Communication can be extended for future progress for improved speed and accuracy.

Keywords

Circuit Switching, 3D NoC, SoC, Packet Switching, Torus, Quality of Service.

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